The present disclosure relates in general to integrated circuit chip fabrication, and more particularly, to a system and method to identify lens aberration patterns in an integrated circuit chip.
In current integrated circuit chip fabrication, a set of test patterns are often used to evaluate lens aberrations. Lens aberrations are deviations from the ideal lens behavior that results from design, fabrication or usage flaws. Typically, an optical proximity correction (OPC) model is used to correct a single layout and a simulation is performed on the corrected layout. The result of the simulation is compared with a designed layout. The difference in the critical dimensions (CDs) between the layouts represents one or more critical dimension errors. Although the detected CD errors are intended to indicate lens aberrations, they may also be due, in part, to inaccuracies of the OPC model. In addition, the set of test patterns used in CD detection may not accurately represent the real layout in a chip and the evaluation often underestimates the impact of lens aberration on CD variations of the actual layouts in a chip.
Therefore, a need exists for a method and system for identifying lens aberration sensitive patterns in an integrated circuit chip, such that the impact of a lens aberration can be isolated and the real layout in a chip can be represented.